Thermal stress optimization of three-dimensional heterogeneous integrated packaging based on silicon through-holes (TSV)
基于硅通孔（TSV）的三维异构集成封装热应力优化研究

摘要

三维异构集成封装借助硅通孔（TSV）技术实现芯片高效互连，大幅提升电子系统性能。TSV 与周围材料热膨胀系数的显著差异，致使热应力问题频发，严重威胁封装可靠性与器件寿命。本文深入剖析基于 TSV 的三维异构集成封装热应力产生根源，通过理论分析与仿真模拟，全面探究热应力分布规律。提出多种创新热应力优化策略，涵盖材料选择、结构设计及热管理等维度，并详细评估其优化效果。研究成果对推动三维异构集成封装技术广泛应用，提升电子设备可靠性与稳定性具有重要意义。

Abstract

Three-dimensional heterogeneous integrated packaging utilizes silicon through-holes (TSV) technology to achieve efficient chip interconnection, significantly enhancing electronic system performance. However, the significant difference in thermal expansion coefficients between TSV and surrounding materials frequently causes thermal stress issues, severely threatening packaging reliability and device lifespan. This paper thoroughly analyzes the root causes of thermal stress generation in TSV-based three-dimensional heterogeneous integrated packaging. Through theoretical analysis and simulation, it comprehensively explores the distribution patterns of thermal stress. Additionally, multiple innovative thermal stress optimization strategies are proposed, covering material selection, structural design, and thermal management dimensions, with detailed evaluation of their optimization effects. The research findings are significant for promoting the widespread application of three-dimensional heterogeneous integrated packaging technology and improving the reliability and stability of electronic devices.